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general description the max1067/max1068 low-power, multichannel, 14- bit analog-to-digital converters (adcs) feature a suc- cessive-approximation adc, integrated +4.096v reference, a reference buffer, an internal oscillator, automatic power-down, and a high-speed spi/ qspi/microwire-compatible interface. the max1067/max1068 operate with a single +5v analog supply and feature a separate digital supply, allowing direct interfacing with +2.7v to +5.5v digital logic. the max1067/max1068 consume only 3.6ma (av dd = dv dd = +5v) at 200ksps when using an external refer- ence. autoshutdown reduces the supply current to 185? at 10ksps and to less than 10? at reduced sam- pling rates. the max1067 includes a 4-channel input multiplexer, and the max1068 accepts up to eight analog inputs. in addition, digital signal processor (dsp)-initiated con- versions are simplified with the dsp frame-sync input and output featured in the max1068. the max1068 includes a data-bit transfer input to select between 8-bit-wide or 16- bit-wide data-transfer modes. both devices feature a scan mode that converts each channel sequentially or one channel continuously. excellent dynamic performance and low power, com- bined with ease of use and an integrated reference, make the max1067/max1068 ideal for control and data- acquisition operations or for other applications with demanding power consumption and space require- ments. the max1067 is available in a 16-pin qsop package, and the max1068 is available in a 24-pin qsop package. both devices are guaranteed over the commercial (0? to +70?) and extended (-40? to +85?) temperature ranges. use the max1168 evalua- tion kit to evaluate the max1068. applications motor control industrial process control industrial i/o modules data-acquisition systems thermocouple measurements accelerometer measurements features ? 14-bit resolution, 0.5 lsb inl and 1 lsb dnl (max) ? +5v single-supply operation ? adjustable logic level (+2.7v to +5.25v) ? input voltage range: 0 to v ref ? internal (+4.096v) or external (+3.8v to av dd ) reference ? internal track/hold, 4mhz input bandwidth ? internal or external clock ? spi/qspi/microwire-compatible serial interface, max1068 performs dsp-initiated conversions ? 8-bit-wide or 16-bit-wide data-transfer mode (max1068 only) ? 4-channel (max1067) or 8-channel (max1068) input mux scan mode sequentially converts multiple channels or one channel continuously ? low power 3.6ma at 200ksps 1.85ma at 100ksps 185a at 10ksps 0.6a in full power-down mode ? small package size 16-pin qsop (max1067) 24-pin qsop (max1068) max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ________________________________________________________________ maxim integrated products 1 ordering information 19-2955; rev 1; 8/07 for pricing delivery, and ordering information please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package inl (lsb) max1067 acee 0? to +70? 16 qsop 0.5 max1067bcee 0? to +70? 16 qsop 1 max1067ccee 0? to +70? 16 qsop 2 max1067aeee -40? to +85? 16 qsop 0.5 MAX1067BEEE -40? to +85? 16 qsop 1 max1067ceee -40? to +85? 16 qsop 2 ordering information continued at end of data sheet. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corp. autoshutdown is a trademark of maxim integrated products, inc. pin configurations appear at end of data sheet.
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v dgnd to agnd.....................................................-0.3v to +0.3v ain_, ref, refcap to agnd..................-0.3v to (av dd + 0.3v) sclk, cs , dsel, dspr, din to dgnd ...................-0.3v to +6v dout, dspx, eoc to dgnd...................-0.3v to (dv dd + 0.3v) maximum current into any pin............................................50ma continuous power dissipation (t a = +70?) 16-pin qsop (derate 8.3mw/? above +70?)...........667mw 24-pin qsop (derate 9.5mw/? above +70?)...........762mw operating temperature ranges max106_ _ ce_ ..................................................0? to +70? max106_ _ ee_ ...............................................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (av dd = dv dd = +4.75v to +5.25v, f sclk = 4.8mhz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units dc accuracy (note 1) resolution 14 bits max106_a ?.5 1 max106_b ?.0 2 relative accuracy (note 2) inl max106_c ?.5 3 lsb max106_a ? max106_b +1.5 -1.0 differential nonlinearity dnl no missing codes over temperature max106_c +1.5 -1.0 lsb external reference 0.33 transition noise rms noise internal reference 0.35 lsb rms offset error ?.1 ?0 mv gain error (note 3) ?.01 ?.2 %fsr offset drift 1 ppm/? gain drift (note 3) ?.2 ppm/? dynamic specifications (1khz sine wave, 4.096v p-p ) (note 1) signal-to-noise plus distortion sinad 81 84 db signal-to-noise ratio snr 82 84 db total harmonic distortion thd -98 -86 db spurious-free dynamic range sfdr 86 99 db full-power bandwidth -3db point 4 mhz full-linear bandwidth sinad > 81db 10 khz channel-to-channel isolation (note 4) 85 db conversion rate internal clock, no data transfer, single conversion (note 5) 5.52 7.07 conversion time t conv external clock 3.75 ?
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd = dv dd = +4.75v to +5.25v, f sclk = 4.8mhz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units acquisition time t acq (note 6) 729 ns external clock, data transfer and conversion 0.1 4.8 serial clock frequency f sclk external clock, data transfer only 9 mhz internal clock frequency f intclk internal clock 3.2 4.0 mhz aperture delay t ad 15 ns aperture jitter t aj <50 ps 8-bit-wide data-transfer mode 4.17 200.00 16-bit-wide data-transfer mode 3.125 150.000 internal clock, single conversion, 8-bit-wide data-transfer mode 89 internal clock, single conversion, 16-bit- wide data-transfer mode 68 internal clock, scan mode, 8-bit-wide data- transfer mode (four conversions) 103 sample rate (note 7) f s external clock, scan mode, 16-bit-wide data-transfer mode (four conversions) 82 ksps duty cycle 45 55 % analog input (ain_) input range v ain _0 v ref v input capacitance c ain _45pf external reference input voltage range v ref (note 8) 3.8 av dd ?0.2 v v ain _ = 0 34 sclk idle 0.1 input current i ref cs = dv dd , sclk idle 0.1 ? internal reference reference voltage v refin 4.042 4.096 4.136 v reference short-circuit current i refsc 13 ma reference temperature coefficient ?5 ppm/? reference wake-up time t rwake v ref = 0 5 ms
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd = dv dd = +4.75v to +5.25v, f sclk = 4.8mhz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units digital inputs (sclk, cs , dsel, dspr, din) (dv dd = +2.7v to +5.25v) input high voltage v ih 0.7 dv dd v input low voltage v il 0.3 = digital output (dout, dspx, eoc ) (dv dd = +2.7v to +5.25v) output high voltage v oh i source = 0.5ma dv dd - 0.4 v i sink = 10ma, dv dd = +4.75v to +5.25v 0.8 output low voltage v ol i sink = 1.6ma, dv dd = +2.7v to +5.25v 0.4 v tri-state output leakage current i l cs = dv dd ?.1 ?0 ? tri-state output capacitance c out cs = dv dd 15 pf power supplies analog supply av dd 4.75 5.25 v digital supply dv dd 2.70 5.25 v external reference 2.7 3.3 200ksps internal reference 3.6 4.2 external reference 1.4 100ksps internal reference 2.7 external reference 0.14 10ksps internal reference 1.8 external reference 0.014 analog supply current (note 9) i avdd 1ksps internal reference 1.7 ma 200ksps 0.87 1.3 100ksps 0.45 10ksps 0.045 digital supply current i dvdd dout = all zeros 1ksps 0.005 ma internal reference and reference buffer on between conversions 0.66 power-down supply current i avdd + i dvdd cs = dv dd , sclk = 0, din = 0, dspr = dv dd internal reference on, reference buffer off between conversions 0.20 ma
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd = dv dd = +4.75v to +5.25v, f sclk = 4.8mhz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units shutdown supply current i avdd + i dvdd cs = dv dd , sclk = 0, din = 0, dspr = dv dd , full power-down 0.6 10 ? power-supply rejection ratio psrr av dd = dv dd = 4.75v to 5.25v, full-scale input (note 10) 63 db timing characteristics (figures 1, 2, 8, and 16) ( av dd = dv dd = +4.75v to +5.25v , f sclk = 4.8mhz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units acquisition time t acq external clock (note 6) 729 ns sclk to dout valid t do c dout = 30pf 50 ns cs fall to dout enable t dv c dout = 30pf 80 ns cs rise to dout disable t tr c dout = 30pf 80 ns cs pulse width t csw 100 ns sclk rise cs to sclk setup t css sclk fall (dsp) 100 ns sclk rise cs to sclk hold t csh sclk fall (dsp) 0ns conversion 93 sclk high pulse width t ch duty cycle 45% to 55% data transfer 50 ns conversion 93 sclk low pulse width t cl duty cycle 45% to 55% data transfer 50 ns sclk period t cp 209 ns sclk rise din to sclk setup t ds sclk fall (dsp) 50 ns sclk rise din to sclk hold t dh sclk fall (dsp) 0ns cs falling to dspr rising t df 100 ns dspr to sclk falling setup t fss 100 ns dspr to sclk falling hold t fsh 0ns
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 6 _______________________________________________________________________________________ timing characteristics (figures 1, 2, 8, and 16) (av dd = +4.75v to +5.25v, dv dd = +2.7v to +5.25v , f sclk = 4.8mhz external clock (50% duty cycle), 24 clocks/conversion (200ksps), external v ref = +4.096v, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units acquisition time t acq external clock (note 6) 729 ns sclk to dout valid t do c dout = 30pf 100 ns cs fall to dout enable t dv c dout = 30pf 100 ns cs rise to dout disable t tr c dout = 30pf 80 ns cs pulse width t csw 100 ns sclk rise cs to sclk setup t css sclk fall (dsp) 100 ns sclk rise cs to sclk hold t csh sclk fall (dsp) 0ns conversion 93 sclk high pulse width t ch duty cycle 45% to 55% data transfer 93 ns conversion 93 sclk low pulse width t cl duty cycle 45% to 55% data transfer 93 ns sclk period t cp 209 ns sclk rise din to sclk setup t ds sclk fall (dsp) 100 ns sclk rise din to sclk hold t dh sclk fall (dsp) 0ns cs falling to dspr rising t df 100 ns dspr to sclk falling setup t fss 100 ns dspr to sclk falling hold t fsh 0ns note 1: av dd = dv dd = +5.0v. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after full-scale range has been calibrated. note 3: offset and reference errors nulled. note 4: dc voltage applied to on channel, and a full-scale 1khz sine wave applied to off channels. note 5: conversion time is measured from the rising edge of the 8th external sclk pulse to eoc transition minus t acq in 8-bit data-transfer mode. note 6: see figures 10 and 17. note 7: f sclk = 4.8mhz, f intclk = 4.0mhz. sample rate is calculated with the formula f s = n 1 (n 2 / f sclk + n 3 / f intclk ) -1 where: n 1 = number of scans, n 2 = number of sclk cycles, and n 3 = number of internal clock cycles (see figures 11?4). note 8: guaranteed by design, not production tested. note 9: internal reference and buffer are left on between conversions. note 10: defined as the change in the positive full scale caused by a ?% variation in the nominal supply voltage.
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters _______________________________________________________________________________________ 7 -1.0 -0.6 -0.4 -0.8 0.2 0 0.4 -0.2 0.6 0.8 1.0 0 8192 4096 12,288 16,384 inl vs. code max1067/68 toc01 code inl (lsb) -1.0 -0.6 -0.4 -0.8 0.2 0 0.4 -0.2 0.6 0.8 1.0 0 8192 4096 12,288 16,384 dnl vs. code max1067/68 toc02 code dnl (lsb) -160 -120 -100 -140 -40 -60 -20 -80 0 20 06080 20 40 100 fft at f ain = 1khz max1067/68 toc03 frequency (khz) amplitude (db) sinad vs. frequency max1067/68 toc04 frequency (khz) sinad (db) 10 1 10 20 30 40 50 60 70 80 90 0 0.1 100 f sample = 200kbps sfdr vs. frequency max1067/68 toc05 frequency (khz) sfdr (db) 10 1 20 40 60 80 100 120 0 0.1 100 f sample = 200ksps thd vs. frequency max1067/68 toc06 frequency (khz) thd (db) 10 1 -100 -80 -60 -40 -20 0 -120 0.1 100 f sample = 200kbps supply current vs. conversion rate (external clock) max1067/68 toc07 conversion rate (ksps) supply current (ma) 180 160 140 120 100 80 60 40 20 0 0.5 1.0 1.5 2.0 2.5 3.0 -0.5 0 200 i avdd , int ref i avdd , ext ref dv dd = av dd = +5v d out = all zeros external clock spi mode i dvdd analog supply current vs. analog supply voltage (internal reference) max1067/68 toc08 av dd (v) i avdd (ma) 5.15 5.05 4.95 4.85 2.75 2.80 2.85 2.90 2.95 2.70 4.75 5.25 dv dd = +5v f s = 200ksps t a = 0 c t a = -40 c t a = +85 c t a = +70 c t a = +25 c analog supply current vs. analog supply voltage (external reference) max1067/68 toc09 av dd (v) i avdd (ma) 5.15 5.05 4.95 4.85 1.80 1.85 1.90 1.95 2.00 1.75 4.75 5.25 t a = 0 c t a = -40 c t a = +85 c t a = +70 c t a = +25 c dv dd = +5v f s = 200ksps typical operating characteristics (av dd = dv dd = +5v, f sclk = 4.8mhz, c dout = 30pf, external v ref = +4.096v, t a = +25?, unless otherwise noted.)
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 8 _______________________________________________________________________________________ digital supply current vs. digital supply voltage max1067/68 toc10 dv dd (v) i dvdd (ma) 4.74 4.23 3.72 3.21 0.6 1.0 1.4 1.8 2.2 2.6 0.2 2.70 5.25 av dd = +5v v il = 0 f s = 200ksps dout = 1010...1010 dout = 0000...0000 power-down supply current vs. av dd supply voltage (internal reference) max1067/68 toc11 av dd (v) i dvdd ( a) i avdd (ma) 5.15 5.05 4.95 4.85 0.53 0.54 0.55 0.56 0.57 0.58 0.52 0.99 1.00 1.01 1.02 1.03 1.04 0.98 4.75 5.25 dv dd = +5v i avdd i dvdd power-down supply current vs. dv dd supply voltage (internal reference) max1067/68 toc12 dv dd (v) i dvdd ( a) i avdd (ma) 4.74 4.23 3.72 3.21 0.2 0.3 0.4 0.5 0.6 0.7 0.1 1.00 1.01 1.02 1.03 0.99 2.70 5.25 dv dd = +5v av dd = +5v i avdd i dvdd shutdown supply current vs. av dd supply voltage (external reference) max1067/68 toc13 av dd (v) i dvdd ( a) i avdd (na) 5.15 5.05 4.95 4.85 0.53 0.54 0.55 0.56 0.57 0.58 0.52 0.34 0.38 0.42 0.46 0.50 0.54 0.30 4.75 5.25 dv dd = +5v i avdd i dvdd shutdown supply current vs. dv dd supply voltage (external reference) max1067/68 toc14 dv dd (v) i dvdd ( a) i avdd (na) 4.74 4.23 3.72 3.21 0.2 0.3 0.4 0.5 0.6 0.7 0.1 0.38 0.39 0.40 0.41 0.42 0.43 0.37 2.70 5.25 dv dd = +5v av dd = +5v i avdd i dvdd power-down supply current vs. temperature (internal reference) max1067/68 toc15 temperature ( c) i dvdd ( a) i avdd (ma) 60 35 10 -15 0.53 0.54 0.55 0.56 0.57 0.58 0.52 0.99 1.00 1.01 1.02 1.03 1.04 0.98 -40 85 dv dd = av dd = +5v i avdd i dvdd shutdown supply current vs. temperature (external reference) max1067/68 toc16 temperature ( c) i dvdd ( a) i avdd (na) 60 35 10 -15 0.53 0.54 0.55 0.56 0.57 0.58 0.52 0.37 0.39 0.41 0.43 0.45 0.35 -40 85 dv dd = av dd = +5v i avdd i dvdd typical operating characteristics (continued) (av dd = dv dd = +5v, f sclk = 4.8mhz, c dout = 30pf, external v ref = +4.096v, t a = +25?, unless otherwise noted.)
offset error vs. supply voltage max1067/68 toc17 av dd (v) offset error ( v) 5.15 4.85 5.05 4.95 -150 -100 -50 0 50 100 150 200 -200 4.75 5.25 v ref = +4.096v gain error vs. supply voltage max1067/68 toc18 av dd (v) gain error (%fsr) 5.15 4.85 5.05 4.95 -0.025 -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 0.020 -0.030 4.75 5.25 v ref = +4.096v max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters _______________________________________________________________________________________ 9 offset error vs. temperature max1067/68 toc19 temperature ( c) offset error ( v) 60 35 10 -15 -400 -300 -200 0 -100 100 200 300 400 500 -500 -40 85 v ref = +4.096v gain error vs. temperature max1067/68 toc20 temperature ( c) gain error (%fsr) 60 35 10 -15 -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 0.015 -0.025 -40 85 v ref = +4.096v channel-to-channel isolation vs. frequency max1067/68 toc21 frequency (khz) isolation (db) 90 80 60 70 20 30 40 50 10 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -110 0100 v ref = +4.096v internal +4.096v reference voltage vs. analog supply voltage max1067/68 toc22 av dd (v) v ref (v) 5.15 5.05 4.95 4.85 4.092 4.096 4.100 4.104 4.088 4.75 5.25 dv dd = +5v t a = 0 c t a = -40 c t a = +85 c t a = +25 c t a = +70 c external reference input current vs. external reference voltage max1067/68 toc23 v ref (v) i ref ( a) 5.0 4.5 2.5 3.0 3.5 4.0 20 40 60 80 100 120 140 160 0 2.0 5.5 v ain = 0 f sclk = 4.8mhz av dd = dv dd = +5v 199ksps, external clock 87.19ksps, internal clock internal reference voltage vs. ref load max1067/68 toc24 i ref (ma) v ref (v) 12 10 6 8 4 2 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 014 f sclk = 0 internal reference mode load applied to ref c ref = 1 f internal clock conversion time (8th rising sclk to falling eoc) max1067/68 toc25 number of scan-mode conversions t conv (ms) 8 7 6 5 4 3 2 10 20 30 40 50 60 70 0 1 f sclk = 4.8mhz 8-bit data-transfer mode 16-bit data-transfer mode 6 10 12 17 17 24 22 31 28 39 33 46 38 53 44 60 typical operating characteristics (continued) (av dd = dv dd = +5v, f sclk = 4.8mhz, c dout = 30pf, external v ref = +4.096v, t a = +25?, unless otherwise noted.)
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 10 ______________________________________________________________________________________ pin description pin max1067 max1068 name function 13 dout serial data output. data changes state on sclk? falling edge in spi/qspi/microwire mode and on sclk? rising edge in dsp mode (max1068 only). dout is high impedance when cs is high. 24 sclk serial clock input. sclk drives the conversion process in external clock mode and clocks data out. 3 5 din serial data input. use din to communicate with the command/configuration/control register. in spi/qspi/microwire mode, the rising edge of sclk clocks in data at din. in dsp mode, the falling edge of sclk clocks in data at din. 46 eoc end-of-conversion output. in internal clock mode, a logic low at eoc signals the end of a conversion with the result available at dout. in external clock mode, eoc remains high. 5 7 ain0 analog input 0 6 8 ain1 analog input 1 7 9 ain2 analog input 2 8 10 ain3 analog input 3 9 15 ref reference voltage input/output. v ref sets the analog voltage range. bypass to agnd with a 10? capacitor. bypass with a 1? (min) capacitor when using the internal reference. 10 16 refcap refer ence byp ass c ap aci tor c onnecti on. byp ass to ag n d w i th a 0.1f cap aci tor w hen usi ng i nter nal r efer ence. inter nal r efer ence and b uffer shut d ow n i n exter nal r efer ence m od e. 11 17 agnd analog ground. connect to pin 18 (max1068) or pin 12 (max1067). 12 18 agnd primary analog ground (star ground). power return for av dd . 13 19 av dd analog supply voltage. bypass to agnd with a 0.1? capacitor. 14 20 cs active-low chip-select input. forcing cs high places the max1067/max1068 in shutdown with a typical supply current of 0.6?. in spi/qspi/microwire mode, a high-to-low transition on cs activates normal operating mode. in dsp mode, after the initial cs transition from high to low, cs can remain low for the entire conversion process (see the operating modes section). 15 21 dgnd digital ground 16 22 dv dd digital supply voltage. bypass to dgnd with a 0.1? capacitor. ? dspr dsp frame-sync receive input. a frame-sync pulse received at dspr initiates a conversion. connect to logic high when using spi/qspi/microwire mode. ? dsel data-bit transfer-select input. logic low on dsel places the device in 8-bit-wide data- transfer mode. logic high places the device in 16-bit-wide data-transfer mode. do not leave dsel unconnected. 11 ain4 analog input 4 12 ain5 analog input 5
detailed description the max1067/max1068 low-power, multichannel, 14- bit adcs feature a successive-approximation adc, automatic power-down, integrated +4.096v reference, and a high-speed spi/qspi/microwire-compatible interface. a dspr input and dspx output allow the max1068 to communicate with dsps with no external glue logic. the max1067/max1068 operate with a sin- gle +5v analog supply and feature a separate digital supply allowing direct interfacing with +2.7v to +5.5v digital logic. figures 3 and 4 show the functional diagrams of the max1067/max1068, and figures 5 and 6 show the max1067/max1068 in a typical operating circuit. the serial interface simplifies communication with micro- processors (?s). in external reference mode, the max1067/max1068 have two power modes: normal mode and shutdown mode. driving cs high places the max1067/max1068 in shutdown mode, reducing the supply current to 0.6? (typ). pull cs low to place the max1067/ max1068 in normal operating mode. the internal refer- ence mode offers software-programmable, power-down options as shown in table 5. in spi/qspi/microwire mode, a falling edge on cs wakes the analog circuitry and allows sclk to clock in data. acquisition and conversion are initiated by sclk. the conversion result is available at dout in unipolar serial format. dout is held low until data becomes available (msb first) on the 8th falling edge of sclk when in 8-bit transfer mode, and on the 16th falling edge when in 16-bit transfer mode. see the operating modes section. figure 8 shows the detailed spi/qspi/ microwire serial-interface timing diagram. in external clock mode, the max1068 also interfaces with dsps. in dsp mode, a frame-sync pulse from the dsp initiates a conversion that is driven by sclk. the max1068 formats a frame-sync pulse to notify the dsp that the conversion results are available at dout in msb-first, unipolar, serial-data format. figure 16 shows the detailed dsp serial-interface timing diagram (see the operating modes section). analog input figure 7 illustrates the input-sampling architecture of the adc. the voltage applied at ref or the internal +4.096v reference sets the full-scale input voltage. track/hold (t/h) in track mode, the analog signal is acquired on the internal hold capacitor. in hold mode, the t/h switches open and the capacitive digital-to-analog converter (dac) samples the analog input. max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 11 pin description (continued) pin max1067 max1068 name function 13 ain6 analog input 6 14 ain7 analog input 7 ?3 dspx dsp frame-sync transmit output. a frame-sync pulse at dspx notifies the dsp that the msb data is available at dout. leave dspx unconnected when not in dsp mode. 24 n.c. no connection. not internally connected. dgnd 1ma c load = 30pf dout dout c load = 30pf 1ma dgnd dv dd a) v ol to v oh b) high-z to v ol and v oh to v ol figure 1. load circuits for dout enable time and sclk-to- dout delay time dgnd 1ma c load = 30pf dout dout c load = 30pf 1ma dgnd dv dd a) v oh to high-z b) v ol to high-z figure 2. load circuits for dout disable time
max1067/max1068 during the acquisition, the analog input (ain_) charges capacitor c dac . at the end of the acquisition interval the t/h switches open. the retained charge on c dac represents a sample of the input. in hold mode, the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to zero within the limits of 14-bit resolution. at the end of the conversion, force cs high and then low to reset the t/h switches back to track mode (ain_), where c dac charges to the input signal again. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the maximum time the device takes to acquire the signal. use the following formula to calculate acqui- sition time: t acq = 11(r s + r in + r ds(on) ) ? 45pf + 0.3? where r in = 340 ? , r s = the input signal? source impedance, r ds(on) = 60 ? , and t acq is never less than 729ns. a source impedance less than 200 ? does not significantly affect the adc? performance. the max1068 features a 16-bit-wide data-transfer mode multichannel, 14-bit, 200ksps analog-to-digital converters 12 ______________________________________________________________________________________ reference ref refcap av dd dv dd agnd agnd dgnd ain0 ain1 ain2 ain3 sclk cs din analog-input multiplexer multiplexer control accumulator memory input register bias oscillator output dout eoc analog-switch fine timing successive-approximation register max1067 dac buffer az rail comparator figure 3. max1067 functional diagram
that includes a longer acquisition time (11.5 clock cycles). longer acquisition times are useful in applica- tions with input source resistances greater than 1k ? . noise increases when using large source resistances. to improve the input signal bandwidth under ac conditions, drive ain_ with a wideband buffer (>10mhz) that can drive the adc? input capacitance and settle quickly. input bandwidth the adc? input-tracking circuitry has a 4mhz small- signal bandwidth, making possible the digitization of high-speed transient events and the measurement of periodic signals with bandwidths exceeding the adc? sampling rate by using undersampling techniques. to avoid aliasing of unwanted, high-frequency signals into the frequency band of interest, use anti-alias filtering. analog input protection internal protection diodes, which clamp the analog input to av dd or agnd, allow the input to swing from (agnd - 0.3v) to (av dd + 0.3v) without damaging the device. if the analog input exceeds 300mv beyond the supplies, limit the input current to 10ma. max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 13 reference ref refcap av dd dv dd agnd agnd dgnd ain0 ain1 ain2 ain3 sclk cs din analog-input multiplexer multiplexer control accumulator memory input register bias oscillator output dout eoc analog-switch fine timing successive-approximation register max1068 dac buffer ain4 ain5 ain6 ain7 az rail comparator dspx dsel dspr figure 4. max1068 functional diagram
max1067/max1068 digital interface the max1067/max1068 feature an spi/qspi/ microwire-compatible 3-wire serial interface. the max1067 digital interface consists of digital inputs cs , sclk, and din; and outputs dout and eoc . the max1067 operates in the following modes: spi interface with external clock spi interface with internal clock spi interface with internal clock and scan mode in addition to the standard 3-wire serial interface modes, the max1068 includes a dspr input and a dspx output for communicating with dsps in external clock mode and a dsel input to determine 8-bit-wide or 16-bit-wide data-transfer mode. when not using the max1068 in the dsp interface mode, connect dspr to dv dd and leave dspx unconnected. command/configuration/control register table 1 shows the contents of the command/configura- tion/control register and the state of each bit after initial power-up. tables 2? define the control and configura- tion of the device for each bit. cycling the power sup- plies resets the command/configuration/control register to the power-on-reset default state. initialization after power-up a logic high on cs places the max1067/max1068 in the shutdown mode chosen by the power-down bits, and places dout in a high-impedance state. drive cs low to power-up and enable the max1067/max1068 before starting a conversion. in internal reference mode, allow 5ms for the shutdown internal reference and/or buffer to wake and stabilize before starting a conversion. in exter- nal reference mode (or if the internal reference is already on), no reference settling time is needed after power-up. multichannel, 14-bit, 200ksps analog-to-digital converters 14 ______________________________________________________________________________________ sclk dout agnd dgnd ain0 ref av dd dv dd dout sclk cs +5v din analog inputs +5v 1 f 0.1 f 0.1 f gnd max1067 0.1 f ain1 ain2 ain3 din eoc eoc agnd refcap cs figure 5. max1067 typical operating circuit sclk dout agnd dgnd ain0 ref av dd dv dd dout sclk cs +5v 16 8 din analog inputs +5v 1 f 0.1 f 0.1 f gnd max1068 0.1 f ain1 ain2 ain3 ain4 ain5 ain6 ain7 din dsel dspr dspx dspx eoc agnd refcap eoc cs figure 6. max1068 typical operating circuit auto-zero rail capacitive dac c dac ref agnd track hold hold track zero mux r in r dson ain_ c mux c switch figure 7. equivalent input circuit bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) command ch sel2 ch sel1 ch sel0 scan1 scan0 ref/pd_sel1 ref/pd sel0 int/ext clk power-up state 00000110 table 1. command/configuration/control register
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 15 bit7 bit6 bit5 ch sel2 ch sel1 ch sel0 channel ain_ 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 table 2. channel select bit4 bit3 action scan1 scan0 single channel, no scan 0 0 sequentially scan channels 0 through n (n 3) 01 sequentially scan channels 2 through n (2 n 3) 10 scan channel n 4 times 1 1 table 3. max1067 scan mode, internal clock only bit4 bit3 action scan1 scan0 single channel, no scan 0 0 sequentially scan channels 0 through n (n 7) 01 sequentially scan channels 4 through n (4 n 7) 10 scan channel n 8 times 1 1 table 4. max1068 scan mode, internal clock only (not for dsp mode) bit2 bit1 ref/pd_ sel1 ref/pd sel0 reference reference mode (internal reference) typical supply current typical wake- up time (c ref = 1?) 0 0 internal internal reference and reference buffer stay on between conversions 1ma na 0 1 internal internal reference and reference buffer off between conversions 0.6? 5ms 1 0 internal internal reference on, reference buffer off between conversions 0.43ma 5ms 1 1 external internal reference and buffer always off 0.6? na table 5. power-down modes bit0 int/ext clk clock mode 0 external clock 1 internal clock table 6. clock modes
max1067/max1068 power-down modes table 5 shows the max1067/max1068 power-down modes. three internal reference modes and one exter- nal reference mode are available. select power-down modes by writing to bits 2 and 1 in the command/con- figuration/control register. the max1067/max1068 enter the selected power-down mode on the rising edge of cs . the internal reference stays on when cs is pulled high, if bits 2 and 1 are set to zero. this mode allows for the fastest turn-on time. setting bit 2 = 0 and bit 1 = 1 turns both the reference and reference buffer off when cs is brought high. this mode achieves the lowest supply current. the refer- ence and buffer wake up on the falling edge of cs when in spi/qspi/microwire mode and on the falling edge of dspr when in dsp mode. allow 5ms for the internal reference to rise and settle when powering up from a complete shutdown (v ref = 0, c ref = 1?). the internal reference stays on and the buffer is shut off on the rising edge of cs when bit 2 = 1 and bit 1 = 0. the max1067/max1068 enter this mode on the rising edge of cs . the buffer wakes up on the falling edge of cs when in spi/qspi/microwire mode and on the falling edge of dspr when in dsp mode. allow 5ms for v ref to settle when powering up from a complete shut- down (v ref = 0, c ref = 1?). v refcap is always equal to +4.096v in this mode. set both bit 2 and bit 1 to 1 to turn off the reference and reference buffer to allow connection of an external ref- erence. using an external reference requires no extra wake-up time. operating modes external clock 8-bit-wide data-transfer mode (max1067 and max1068) force dspr high and dsel low (max1068) for spi/ qspi/microwire-interface mode. the falling edge of cs wakes the analog circuitry and allows sclk to clock in data. ensure the duty cycle on sclk is between 45% and 55% when operating at 4.8mhz (the maximum clock fre- quency). for lower clock frequencies, ensure the multichannel, 14-bit, 200ksps analog-to-digital converters 16 ______________________________________________________________________________________ cs sclk din dout t csw t css t cl t ds t dh t dv t ch t do t tr t csh t cp ? ? ? ? ? ? ? ? ? ? ? ? figure 8. detailed spi interface timing complete conversion sequence conversion 0 conversion 1 powered up powered up powered down dout cs figure 9. shutdown sequence
minimum high and low times are at least 93ns. external clock-mode conversions with sclk rates less than 125khz can reduce accuracy due to leakage of the sam- pling capacitor. dout changes from high-z to logic low after cs is brought low. input data latches on the rising edge of sclk. the first sclk rising edge begins loading data into the command/configuration/control register from din. the devices select the proper channel for conver- sion on the rising edge of the 3rd sclk cycle. acquisition begins immediately thereafter and ends on the falling edge of the 6th clock cycle. the max1067/max1068 sample the input and begin conversion on the falling edge of the 6th clock cycle. setup and configuration of the max1067/max1068 complete on the rising edge of the 8th clock cycle. the conversion result is available (msb first) at dout on the falling edge of the 8th sclk cycle. to read the entire conversion result, 16 sclk cycles are needed. extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of cs, cause zeros to be clocked out of dout. the max1067/max1068 external clock 8-bit-wide data-transfer mode requires 24 sclk cycles for comple- tion (figure 10). force cs high after the conversion result is read. for maximum throughput, force cs low again to initiate the next conversion immediately after the specified mini- mum time (t csw ). forcing cs high in the middle of a conversion immediately aborts the conversion and places the max1067/max1068 in shutdown. external clock 16-bit-wide data-transfer mode (max1068 only) force dspr high and dsel high for spi/qspi/ microwire-interface mode. logic high at dsel allows the max1068 to transfer data in 16-bit-wide words. the acquisition time is extended an extra eight sclk cycles in the 16-bit-wide data-transfer mode. the falling edge of cs wakes the analog circuitry and allows sclk to clock in data. ensure the duty cycle on sclk is between 45% and 55% when operating at 4.8mhz (the maximum clock frequency). for lower clock frequen- cies, ensure that the minimum high and low times are at least 93ns. external-clock-mode conversions with sclk rates less than 125khz can reduce accuracy due to leakage of the sampling capacitor. dout changes from high-z to logic low after cs is brought low. input data latches on the rising edge of sclk. the first sclk rising edge begins loading data into the command/configura- tion/control register from din. the devices select the proper channel for conversion and begin acquisition on the rising edge of the 3rd sclk cycle. setup and con- figuration of the max1068 completes on the rising edge of the 8th clock cycle. acquisition ends on the falling edge of the 14th sclk cycle. the max1068 samples the input and begins conversion on the falling edge of the 14th clock cycle. the conversion result is available (msb first) at dout on the falling edge of the 16th sclk cycle. to read the entire conversion result, 16 sclk cycles are needed. extra clock pulses, occurring after the conversion result has been clocked out and max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 17 dout cs sclk din dspr* *max1068 only 0 msb lsb msb lsb s1 s0 t acq idle t conv adc state 1 8 16 24 dsel* figure 10. spi external clock mode, 8-bit data-transfer mode, conversion timing
max1067/max1068 prior to the rising edge of cs , cause zeros to be clocked out of dout. the max1068 external clock 16- bit-wide data-transfer mode requires 32 sclk cycles for completion (figure 11). force cs high after the conversion result is read. for maximum throughput, force cs low again to initiate the next conversion immediately after the specified mini- mum time (t csw ). forcing cs high in the middle of a conversion immediately aborts the conversion and places the max1068 in shutdown. internal clock 8-bit-wide data-transfer and scan mode (max1067 and max1068) force dspr high and dsel low (max1068) for the spi/ qspi/microwire-interface mode. the falling edge of cs wakes the analog circuitry and allows sclk to clock in data (figure 12). dout changes from high-z to logic low after cs is brought low. input data latches on the rising edge of sclk. the command/configura- tion/control register begins reading din on the first sclk rising edge and ends on the rising edge of the 8th sclk cycle. the max1067/max1068 select the proper channel for conversion on the rising edge of the 3rd sclk cycle. the internal oscillator activates 125ns after the rising edge of the 8th sclk cycle. turn off the external clock while the internal clock is on. turning off sclk ensures the lowest noise performance during acquisition. acquisition begins on the 2nd rising edge of the internal clock and ends on the falling edge of the 6th internal clock cycle. each bit of the conversion result shifts into memory as it becomes available. the conversion result is available (msb first) at dout on the falling edge of eoc . the internal oscillator and ana- log circuitry are shut down on the high-to-low eoc tran- multichannel, 14-bit, 200ksps analog-to-digital converters 18 ______________________________________________________________________________________ dout cs sclk din dspr dsel 0 msb lsb msb lsb s1 s0 adc state 16 24 32 1 8 x x x x x x xx x = don , t care t acq idle t conv figure 11. spi external clock mode, 16-bit data-transfer mode, conversion timing (max1068 only) dout cs sclk din eoc 1 msb lsb lsb s1 s0 x t acq idle t conv power-down adc state x = don , t care dspr = dv dd , dsel = gnd (max1068 only) internal clk 1 8 26 25 16 924 ? ? ? msb figure 12. spi internal clock mode, 8-bit data-transfer mode, conversion timing
sition. use the eoc high-to-low transition as the signal to restart the external clock (sclk). to read the entire conversion result, 16 sclk cycles are needed. extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of cs, cause the conversion result to be shifted out again. the max1067/max1068 internal clock 8-bit-wide data- transfer mode requires 24 external clock cycles and 25 internal clock cycles for completion. force cs high after the conversion result is read. for maximum throughput, force cs low again to initiate the next conversion immediately after the specified mini- mum time (t csw ). forcing cs high in the middle of a conversion immediately aborts the conversion and places the max1067/max1068 in shutdown. scan mode allows multiple channels to be scanned consecutively or one channel to be scanned eight times. scan mode can only be enabled when using the max1067/max1068 in the internal clock mode. enable scanning by setting bits 4 and 3 in the command/con- figuration/control register (see tables 3 and 4). in scan mode, conversion results are stored in memory until the completion of the last conversion in the sequence. upon completion of the last conversion in the sequence, eoc transitions from high to low to indicate the end of the conversion and shuts down the internal oscillator. use the eoc high-to-low transition as the sig- nal to restart the external clock (sclk). dout provides the conversion results in the same order as the channel conversion process. the msb of the first conversion is available at dout on the falling edge of eoc (figure 14). max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 19 dout cs sclk din eoc x x x x x x x x data lsb s1 s0 x t acq configuration x = don , t care dspr = dsel = dv dd t conv power-down adc state internal clk 1 89 16 21332 24 17 32 ? ? ? ? ? ? ? ? ? ? ? ? msb figure 13. spi internal clock mode,16-bit data-transfer mode, conversion timing (max1068 only) dout cs sclk din eoc adc state internal clk 1 8 940 ? ? ? ? ? ? 2 6 24 48 30 26 ? ? ? ? ? ? 1 msb lsb lsb s1 s0 x msb t acq configuration power-down t conv t acq t conv x = don , t care dspr = dv dd , dsel = gnd (max1068 only) figure 14. spi internal clock mode, 8-bit data-transfer mode, scan mode for two conversions, conversion timing
max1067/max1068 internal clock 16-bit-wide data-transfer and scan mode (max1068 only) force dspr high and dsel low for the spi/qspi/ microwire-interface mode. the falling edge of cs wakes the analog circuitry and allows sclk to clock in data (see figure 13). dout changes from high-z to logic low after cs is brought low. input data latches on the ris- ing edge of sclk. the command/configuration/control register begins reading din on the first sclk rising edge and ends on the rising edge of the 8th sclk cycle. the max1068 selects the proper channel for conversion on the rising edge of the 3rd sclk cycle. the internal oscillator activates 125ns after the rising edge of the 16th sclk cycle. turn off the external clock while the internal clock is on. turning off sclk ensures lowest noise performance during acquisition. acquisition begins on the 2nd rising edge of the inter- nal clock and ends on the falling edge of the 18th inter- nal clock cycle. each bit of the conversion result shifts into memory as it becomes available. the conversion result is available (msb first) at dout on the falling edge of eoc . the internal oscillator and analog circuit- ry are shut down on the eoc high-to-low transition. use the eoc high-to-low transition as the signal to restart the external clock (sclk). to read the entire conver- sion result, 16 sclk cycles are needed. extra clock pulses, occurring after the conversion result has been clocked out and prior to the rising edge of cs, cause the conversion result to be shifted out again. the max1068 internal-clock 16-bit-wide data-transfer mode requires 32 external clock cycles and 32 internal clock cycles for completion. force cs high after the conversion result is read. for maximum throughput, force cs low again to initiate the next conversion immediately after the specified mini- mum time (t csw ). forcing cs high in the middle of a conversion immediately aborts the conversion and places the max1068 in shutdown. scan mode allows multiple channels to be scanned consecutively or one channel to be scanned eight times. scan mode can only be enabled when using the max1068 in internal clock mode. enable scanning by setting bits 4 and 3 in the command/configuration/con- trol register (see tables 3 and 4). in scan mode, conver- sion results are stored in memory until the completion of the last conversion in the sequence. upon completion of the last conversion in the sequence, eoc transitions from high to low to indicate the end of the conversion and shuts down the internal oscillator. use the eoc high-to-low transition as the signal to restart the external clock (sclk). dout provides the conversion results in the same order as the channel conversion process. the msb of the first conversion is available at dout on the falling edge of eoc . figure 15 shows the timing dia- gram for 16-bit-wide data transfer in scan mode. multichannel, 14-bit, 200ksps analog-to-digital converters 20 ______________________________________________________________________________________ dout cs sclk din eoc adc state internal clk 1 89 16 ? ? ? ? ? ? ? ? ? ? ? ? x = don , t care 2 13 17 45 48 64 32 34 ? ? ? ? ? ? x x x x x x x x data lsb s1 s0 x ? ? ? ? ? ? t acq power-down t conv t acq t conv msb figure 15. spi internal clock mode, 16-bit data-transfer mode, scan mode for two conversions, conversion timing (max1068 only)
dsp 8-bit-wide data-transfer mode (external clock mode, max1068 only) figure 16 shows the dsp-interface timing diagram. logic low at dspr on the falling edge of cs enables dsp interface mode. after the max1068 enters dsp mode, cs can remain low for the duration of the con- version process and each subsequent conversion. drive dsel low to select the 8-bit data-transfer mode. a sync pulse from the dsp at dspr wakes the analog circuitry and allows sclk to clock in data (figure 17). the frame sync pulse alerts the max1068 that incom- ing data is about to be sent to din. ensure the duty cycle on sclk is between 45% and 55% when operat- ing at 4.8mhz (the maximum clock frequency). for lower clock frequencies, ensure the minimum high and low times are at least 93ns. external clock mode con- versions with sclk rates less than 125khz can reduce accuracy due to leakage of the sampling capacitor. the input data latches on the falling edge of sclk. the command/configuration/control register starts reading data in on the falling edge of the first sclk cycle imme- diately following the falling edge of the frame sync pulse and ends on the falling edge of the 8th sclk cycle. the max1068 selects the proper channel for conversion on the falling edge of the 3rd clock cycle and begins acquisition. acquisition continues until the rising edge of the 7th clock cycle. the max1068 sam- ples the input on the rising edge of the 7th clock cycle. on the rising edge of the 8th clock cycle, the max1068 outputs a frame sync pulse at dspx. the frame sync pulse alerts the dsp that the conversion results are about to be output at dout (msb first) starting on the rising edge of the 9th clock pulse. to read the entire conversion results, 16 sclk cycles are needed. extra clock pulses, occuring after the conversion result has been clocked out, and prior to the next rising edge of dspr, cause zeros to be clocked out of dout. the max1068 external-clock, dsp 8-bit-wide data-transfer mode requires 24 clock cycles to complete. begin a new conversion by sending a new frame sync pulse to dspr followed by new configuration data. send the new dspr pulse immediately after reading the conversion result to realize maximum throughput. sending a new frame sync pulse in the middle of a con- version immediately aborts the current conversion and begins a new one. a rising edge on cs in the middle of a conversion aborts the current conversion and places the max1068 in shutdown. dsp 16-bit-wide data-transfer mode (external clock mode, max1068 only) figure 16 shows the dsp-interface timing diagram. logic low at dspr on the falling edge of cs enables dsp inter- face mode. after the max1068 enters dsp mode, cs can remain low for the duration of the conversion process and each subsequent conversion. the acquisi- tion time is extended an extra eight sclk cycles in the 16-bit-wide data-transfer mode. drive dsel high to select the 16-bit-wide data-transfer mode. a sync pulse from the dsp at dspr wakes the analog circuitry and allows sclk to clock in data (figure 18). the frame sync pulse also alerts the max1068 that incoming data is about to be sent to din. ensure the duty cycle on sclk is between 45% and 55% when operating at max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 21 cs sclk dspr din dout t css t cl t ds t dh t dv t ch t do t tr t fsh t csh t df t cp t csw t fss ... ... ... ... ... figure 16. detailed dsp-interface timing (max1068 only)
max1067/max1068 4.8mhz (the maximum clock frequency). for lower clock frequencies, ensure the minimum high and low times are at least 93ns. external-clock-mode conver- sions with sclk rates less than 125khz can reduce accuracy due to leakage of the sampling capacitor. the input data latches on the falling edge of sclk. the command/configuration/control register starts reading data in on the falling edge of the first sclk cycle imme- diately following the falling edge of the frame sync pulse and ends on the falling edge of the 16th sclk cycle. the max1068 selects the proper channel for conversion on the falling edge of the 3rd clock cycle and begins acquisition. acquisition continues until the rising edge of the 15th clock cycle. the max1068 sam- ples the input on the rising edge of the 15th clock cycle. on the rising edge of the 16th clock cycle, the max1068 outputs a frame sync pulse at dspx. the frame sync pulse alerts the dsp that the conversion results are about to be output at dout (msb first) starting on the rising edge of the 17th clock pulse. to read the entire conversion result, 16 sclk cycles are needed. extra clock pulses, occuring after the conversion result has been clocked out and prior to the next rising edge of dspr, cause zeros to be clocked out of dout. the max1068 external clock, dsp 16-bit-wide data-transfer mode requires 32 clock cycles to complete. begin a new conversion by sending a new frame sync pulse to dspr followed by new configuration data. send the new dspr pulse immediately after reading the conversion result to realize maximum throughput. sending a new frame sync pulse in the middle of a con- version immediately aborts the current conversion and begins a new one. a rising edge on cs in the middle of a conversion aborts the current conversion and places the max1068 in shutdown. multichannel, 14-bit, 200ksps analog-to-digital converters 22 ______________________________________________________________________________________ dout cs dspr sclk din dspx 0 msb lsb msb lsb s1 s0 t acq idle t conv adc state 1 8 16 24 figure 17. dsp external clock mode, 8-bit data-transfer mode, conversion timing (max1068 only) dout cs sclk din 0 msb lsb msb lsb s1 adc state 16 24 32 1 8 x x x x x x xx x = don , t care t acq idle t conv dspr dspx s0 figure 18. dsp external clock mode, 16-bit data-transfer mode, conversion timing (max1068 only)
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 23 output coding and transfer function the data output from the max1067/max1068 is straight binary. figure 19 shows the nominal transfer function. code transitions occur halfway between suc- cessive integer lsb values (v ref = +4.096v, and 1 lsb = +250? or 4.096v / 16,384v). applications information internal reference the internal bandgap reference provides a buffered +4.096v. bypass refcap with a 0.1? capacitor to agnd and ref with a 1? capacitor to agnd. for best results, use low-esr, x5r/x7r ceramic capacitors. allow 5ms for the reference and buffer to wake up from full power-down (see table 5). external reference the max1067/max1068 accept an external reference with a voltage range between +3.8v and av dd . connect the external reference directly to ref. bypass ref to agnd with a 10? capacitor. when not using a low-esr bypass capacitor, use a 0.1? ceramic capac- itor in parallel with the 10? capacitor. noise on the ref- erence degrades conversion accuracy. the input impedance at ref is 37k ? for dc currents. during a conversion, the external reference at ref must deliver 118? of dc load current and have an output impedance of 10 ? or less. for optimal performance, buffer the reference through an op amp and bypass the ref input. consider the equivalent input noise (82v rms ) of the max1067/ max1068 when choosing a reference. internal/external oscillator select either an external (0.1mhz to 4.8mhz) or the internal 4mhz (typ) clock to perform conversions (table 6). the external clock shifts data in and out of the max1067/max1068 in either clock mode. when using the internal clock mode, the internal oscil- lator controls the acquisition and conversion process- es, while the external oscillator shifts data in and out of the max1067/max1068. turn off the external clock (sclk) when the internal clock is on to realize lowest noise performance. the internal clock remains off in external clock mode. input buffer most applications require an input-buffer amplifier to achieve 14-bit accuracy. the input amplifier must have a slew rate of at least 2v/? and a unity-gain bandwidth of at least 10mhz to complete the required output-volt- age change before the end of the acquisition time. at the beginning of the acquisition, the internal sam- pling capacitor array connects to ain_ (the amplifier input), causing some disturbance on the output of the buffer. ensure the sampled voltage has settled before the end of the acquisition time. digital noise digital noise can couple to ain_ and ref. the conver- sion clock (sclk) and other digital signals active during input acquisition contribute noise to the conversion result. noise signals, synchronous with the sampling interval, result in an effective input offset. asynchronous signals produce random noise on the input, whose high- frequency components can be aliased into the frequen- cy band of interest. minimize noise by presenting a low impedance (at the frequencies contained in the noise signal) at the inputs. this requires bypassing ain_ to agnd, or buffering the input with an amplifier that has a small-signal bandwidth of several megahertz (doing both is preferable). ain has a typical bandwidth of 4mhz. output code full-scale transition 11...111 12 3 0 fs fs - 3/2 lsb fs = v ref input voltage (lsb) 1 lsb = v ref 16,384 11...110 11...101 00...011 00...010 00...001 00...000 figure 19. unipolar transfer function, full scale (fs) = v ref , zero scale (zs) = gnd
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 24 ______________________________________________________________________________________ distortion avoid degrading dynamic performance by choosing an amplifier with distortion much less than the total harmonic distortion of the max1067/max1068 at the frequencies of interest (thd = -98db at 1khz). if the chosen amplifier has insufficient common-mode rejection, which results in degraded thd performance, use the inverting configura- tion (positive input grounded) to eliminate errors from this source. low-temperature-coefficient, gain-setting resis- tors reduce linearity errors caused by resistance changes due to self-heating. to reduce linearity errors due to finite amplifier gain, use amplifier circuits with suf- ficient loop gain at the frequencies of interest.. dc accuracy to improve dc accuracy, choose a buffer with an offset much less than the max1067/max1068s?offset (?0mv max for +5v supply), or whose offset can be trimmed while maintaining stability over the required tempera- ture range. serial interfaces spi and microwire interfaces when using the spi (figure 20a) or microwire (figure 20b) interfaces, set cpol = 0 and cpha = 0. drive cs low to power on the max1067/max1068 before starting a conversion (figure 20c). three consecutive 8-bit-wide readings are necessary to obtain the entire 14-bit result from the adc. dout data transitions on the serial clock? falling edge. the first 8-bit-wide data stream contains all leading zeros. the 2nd 8-bit-wide data stream contains the msb through d6. the 3rd 8-bit-wide data stream con- tains d5 through d0 followed by s1 and s0. cs sclk dout i/o sck miso spi v dd ss max1067 max1068 figure 20a. spi connections max1067 max1068 cs microwire sclk dout i/o sk si figure 20b. microwire connections dout* cs sclk 1st byte read 2nd byte read *when cs is high, dout = high-z msb high-z 3rd byte read lsb s1 s0 d5 d4 d3 d2 d1 d0 24 20 16 12 8 6 4 1 d13 d12 d11 d10 d9 d8 d7 d6 d5 0 0000000 figure 20c. spi/microwire interface timing sequence (cpol = cpha = 0)
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 25 qspi interface using the high-speed qspi interface with cpol = 0 and cpha = 0, the max1067/max1068 support a maximum f sclk of 4.8mhz. figure 21a shows the max1067/max1068 connected to a qspi master and figure 21b shows the associated interface timing. pic16 with ssp module and pic17 interface the max1067/max1068 are compatible with a pic16/ pic17 controller (?), using the synchronous serial-port (ssp) module. to establish spi communication, connect the controller as shown in figure 22a and configure the pic16/pic17 as system master by initializing its synchronous serial- port control register (sspcon) and synchronous serial- port status register (sspstat) to the bit patterns shown in tables 7 and 8. in spi mode, the pic16/pic17 ?s allow 8 bits of data to be synchronously transmitted and received simultane- ously. three consecutive 8-bit-wide readings (figure 22b) are necessary to obtain the entire 14-bit result from the adc. dout data transitions on the serial clock? falling edge and is clocked into the ? on sclk? rising edge. the first 8-bit-wide data stream contains all zeros. the 2nd 8-bit-wide data stream contains the msb through d6. the 3rd 8-bit-wide data stream contains bits d5 through d0 followed by s1 and s0. dout* cs sclk *when cs is high, dout = high-z msb 20 16 d13 d12 d11 d10 d9 d8 d7 high-z s1 s0 24 12 14 8 6 d6 d3 d2 d1 lsb d5 d4 sampling instant d0 figure 21b. qspi interface timing sequence (external clock, 8-bit data transfer, cpol = cpha = 0) control bit settings synchronous serial-port control register (sspcon) wcol bit7 x write collision detection bit sspov bit6 x receive overflow detection bit sspen bit5 1 synchronous serial-port enable bit: 0: disables serial port and configures these pins as i/o port pins. 1: enables serial port and configures sck, sdo, and sci pins as serial port pins. ckp bit4 0 clock polarity select bit. ckp = 0 for spi master-mode selection. sspm3 bit3 0 sspm2 bit2 0 sspm1 bit1 0 sspm0 bit0 1 synchronous serial-port mode select bit. sets spi master-mode and selects f clk = f osc / 16. table 7. detailed sspcon register contents x = don? care. qspi sclk dout cs sck miso v dd ss cs max1067 max1068 figure 21a. qspi connections
dsp interface the dsp mode of the max1068 only operates in exter- nal clock mode. figure 23 shows a typical dsp interface connection to the max1068. use the same oscillator as the dsp to provide the clock signal for the max1068. the dsp provides the falling edge at cs to wake the max1068. the max1068 detects the state of dspr on the falling edge of cs (figure 17). logic low at dspr places the max1068 in dsp mode. after the max1068 enters dsp mode, cs can be left low. a frame sync pulse from the dsp to dspr initiates a conversion. the max1068 sends a frame sync pulse from dspx to the dsp signaling that the msb is available at dout. send another frame sync pulse from the dsp to dspr to begin the next conversion. the max1068 does not operate in scan mode when using dsp mode. max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 26 ______________________________________________________________________________________ dout* cs sclk 1st byte read 2nd byte read *when cs is high, dout = high-z msb high-z 3rd byte read lsb s1 s0 d5 d4 d3 d2 d1 d0 24 20 16 12 8 6 4 1 d13 d12 d11 d10 d9 d8 d7 d6 0 0000000 figure 22b. spi interface timing with pic16/pic17 in master mode (cke = 1, ckp = 0, smp = 0, sspm3 - sspm0 = 0001) sck sdi gnd pic16/17 i/o sclk dout cs v dd v dd max1067 max1068 figure 22a. spi interface connection for a pic16/pic17 control bit settings synchronous serial-port status register (sspstat) smp bit7 0 spi data-input sample phase. input data is sampled at the middle of the data output time. cke bit6 1 spi clock edge-select bit. data is transmitted on the rising edge of the serial clock. d/a bit5 x data address bit p bit4 x stop bit s bit3 x start bit r/w bit2 x read/write bit information ua bit1 x update address bf bit0 x buffer-full status bit table 8. detailed sspstat register contents x = don? care.
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 27 definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static linearity parameters for the max1067/max1068 are measured using the end-point method. differential nonlinearity differential nonlinearity (dnl) is the difference between an actual step-width and the ideal value of ? lsb. a dnl error specification of ? lsb guarantees no miss- ing codes and a monotonic transfer function. aperture definitions aperture jitter (t aj ) is the sample-to-sample variation in the time between samples. aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when the actual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (snr) is the ratio of the full-scale analog input (rms value) to the rms quanti- zation error (residual error). the ideal, theoretical mini- mum analog-to-digital noise is caused by quantization noise error only and results directly from the adc? res- olution (n bits): snr = (6.02 ? n + 1.76)db in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms equivalent of all the other adc output signals: sinad (db) = 20 ? log [signal rms / (noise + distortion) rms ] effective number of bits effective number of bits (enob) indicates the global accuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the full- scale range of the adc, calculate the enob as follows: enob = (sinad - 1.76) / 6.02 figure 24 shows the enob as a function of the max1067/ max1068s?input frequency. dsp external clock sclk dspr dspx din dout sclk tfs rfs dt dr fl1 cs max1068 figure 23. dsp interface connection 0.1 10 100 frequency (khz) effective bits 1 14 16 0 2 4 6 8 12 10 f sample = 200ksps effective number of bits (enob) figure 24. effective bits vs. frequency
total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 through v 5 are the 2nd- through 5th-order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of the rms amplitude of the fundamental (maximum signal component) to the rms value of the next-largest fre- quency component. supplies, layout, grounding, and bypassing use printed circuit (pc) boards with separate analog and digital ground planes. do not use wire-wrap boards. connect the two ground planes together at the max1067/max1068 agnd terminal. isolate the digital supply from the analog with a low-value resistor (10 ? ) or ferrite bead when the analog and digital supplies come from the same source (figure 25). constraints on sequencing the power supplies and inputs are as follows: apply agnd before dgnd. apply ain_ and ref after av dd and agnd are present. ?v dd is independent of the supply sequencing. ensure that digital return currents do not pass through the analog ground and that return-current paths are low impedance. a 5ma current flowing through a pc board ground trace impedance of only 0.05 ? creates an error voltage of about 250? and a 1 lsb error with a +4.096v full-scale system. the board layout should ensure that digital and analog signal lines are kept separate. do not run analog and dig- ital lines (especially the sclk and dout) parallel to one another. if one must cross another, do so at right angles. the adc? high-speed comparator is sensitive to high- frequency noise on the av dd power supply. bypass an excessively noisy supply to the analog ground plane with a 0.1? capacitor in parallel with a 1f to 10? low-esr capacitor. keep capacitor leads short for best supply-noise rejection. t +v +v +v 23 2 4 2 5 2 1 hd v v = ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 2 log max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters 28 ______________________________________________________________________________________ sclk dout agnd dgnd ain_ ref av dd dv dd dout sclk cs ain_ +5v 10 ? 1 f 0.1 f 0.1 f gnd max1067 max1068 agnd cs figure 25. powering av dd and dv dd from a single supply
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters ______________________________________________________________________________________ 29 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 dout dv dd dgnd cs av dd agnd agnd refcap ref top view max1067 qsop qsop sclk din ain1 eoc ain0 ain2 ain3 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 n.c. dspx dv dd dgnd sclk dout dsel dspr cs av dd agnd agnd ain1 ain0 eoc din 16 15 14 13 9 10 11 12 refcap ref ain7 ain6 ain5 ain4 ain3 ain2 max1068 pin configurations chip information transistor count: 20,760 process: bicmos ordering information (continued) part temp range pin- package inl (lsb) max1068 aceg 0? to +70? 24 qsop 0.5 max1068bceg 0? to +70? 24 qsop 1 max1068cceg 0? to +70? 24 qsop 2 max1068aeeg* -40? to +85? 24 qsop 0.5 max1068beeg* -40? to +85? 24 qsop 1 max1068ceeg* -40? to +85? 24 qsop 2 * future product?ontact factory for availability.
max1067/max1068 multichannel, 14-bit, 200ksps analog-to-digital converters maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 30 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. qsop.eps f 1 1 21-0055 package outline, qsop .150", .025" lead pitch package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) revision history pages changed at rev 1: 1?, 30

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